Semiconductor devices

ABSTRACT

Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of and claims priorityfrom U.S. patent application Ser. No. 16/422,199, now U.S. Pat. No.10,930,648, filed May 24, 2019, which is a continuation application ofand claims priority from U.S. patent application Ser. No. 15/926,572,now U.S. Pat. No. 10,347,627, filed on Mar. 20, 2018, which claimspriority under 35 U.S.C. § 119 to Korean Patent Application No.10-2017-0075059, filed on Jun. 14, 2017, in the Korean IntellectualProperty Office, the entire contents of which are hereby incorporated byreference herein.

BACKGROUND

The present disclosure relates to semiconductor devices and, moreparticularly, to semiconductor devices including a field effecttransistor. A semiconductor device may include an integrated circuithaving metal oxide semiconductor field effect transistors (MOSFETs). Asthe semiconductor device becomes highly integrated, MOSFETs may bescaled-down in size, which may result in deterioration of operatingcharacteristics of the semiconductor device. For example, a processmargin (e.g., spacing) of metal lines in the semiconductor device maydecrease, which may result in deterioration of operatingcharacteristics. Accordingly, various research has been developed tomanufacture semiconductor devices having high performance whileovercoming limitations due to the high integration of semiconductordevices.

SUMMARY

Some embodiments of the inventive concepts provide a semiconductordevice including highly-integrated field effect transistors. Otherobjects of the present inventive concepts that have not been mentionedabove, however, will be clearly understood by those skilled in the artfrom the following description.

According to example embodiments of the inventive concepts, asemiconductor device may include a plurality of active patternsextending in a first direction. The semiconductor device may include aplurality of gate structures crossing the active patterns and extendingin a second direction crossing the first direction. The semiconductordevice may include a device isolation layer extending in the seconddirection between adjacent first and second ones of the plurality ofgate structures. The semiconductor device may include a plurality ofcontact patterns between the plurality of gate structures and the deviceisolation layer. The semiconductor device may include a plurality ofconnection patterns connected to the plurality of contact patterns,respectively. The device isolation layer may be between the plurality ofconnection patterns, and the plurality of connection patterns may bespaced apart from each other by a first distance in the first direction.The semiconductor device may include a plurality of wiring patternsconnected to the plurality of connection patterns, respectively.Moreover, the device isolation layer may be between the plurality ofwiring patterns, and the plurality of wiring patterns may be spacedapart from each other in the first direction by a second distance thatis longer than the first distance.

A semiconductor device, according to some embodiments, may include aplurality of active patterns extending in a first direction. Thesemiconductor device may include a device isolation layer crossing theplurality of active patterns and extending in a second directioncrossing the first direction. The semiconductor device may include agate structure spaced apart from the device isolation layer andextending in the second direction to cross the plurality of activepatterns. The semiconductor device may include a plurality ofsource/drain impurity layers on the plurality of active patterns onopposite sides of the gate structure. The semiconductor device mayinclude a contact pattern connected to one of the plurality ofsource/drain impurity layers that is between the device isolation layerand the gate structure. The semiconductor device may include aconnection pattern connected to the contact pattern and spaced apart bya first distance in the first direction from an axis that is alignedwith the device isolation layer. Moreover, the semiconductor device mayinclude a wiring pattern connected to the connection pattern and spacedapart in the first direction from the axis that is aligned with thedevice isolation layer by a second distance that is longer than thefirst distance.

A semiconductor device, according to some embodiments, may include asubstrate including a first cell region that includes a first N-wellregion and a first P-well region and a second cell region that includesa second N-well region and a second P-well region. The semiconductordevice may include a gate structure on the first cell region of thesubstrate. The semiconductor device may include first and secondsource/drain impurity regions on the substrate adjacent opposite firstand second sides, respectively, of the gate structure. The semiconductordevice may include a third source/drain impurity region on the secondcell region of the substrate. The semiconductor device may include afirst contact connected to the first source/drain impurity region andincluding a first metallic material. The semiconductor device mayinclude a first connector that contacts the first contact and extends tooverlap at least a portion of the gate structure. The first connectormay include a second metallic material different from the first metallicmaterial. The semiconductor device may include a second contactconnected to the third source/drain impurity region. Moreover, thesemiconductor device may include a second connector that contacts thesecond contact.

Details of other example embodiments are included in the description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a simplified plan view showing a semiconductor deviceaccording to example embodiments of the inventive concepts.

FIG. 2 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts.

FIGS. 3A, 3B, 3C, and 3D illustrate cross-sectional views respectivelytaken along lines I-I′, and IV-IV′ of FIG. 2.

FIG. 4 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts.

FIG. 5 illustrates a cross-sectional view taken along line I-I′ of FIG.4.

FIG. 6 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts.

FIGS. 7, 9, and 11 illustrate plan views showing a portion of asemiconductor device according to example embodiments of the inventiveconcepts.

FIGS. 8, 10, and 12 illustrate cross-sectional views taken along lineI-I′ of FIGS. 7, 9, and 11, respectively.

FIG. 13 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts.

FIG. 14 illustrates a cross-sectional view taken along line I-I′ of FIG.13.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to example embodiments ofthe inventive concepts will be described in detail in conjunction withthe accompanying drawings.

FIG. 1 illustrates a simplified plan view showing a semiconductor deviceaccording to example embodiments of the inventive concepts.

Referring to FIG. 1, a semiconductor substrate 100 may be providedthereon with a plurality of integrated standard cells SC including logicdevices such as a logical sum gate or a logical product gate. Forexample, the standard cells SC may include a basic cell (e.g., an ANDgate, an OR gate, a NOR, or an inverter), a complex cell (e.g., OAI(OR/AND/Inverter) gates and AOI (AND/OR/Inverter) gates), or a storageelement (e.g., a master-slave flip-flop and a latch).

The standard cells SC may be two-dimensionally arranged along a firstdirection D1 and a second direction D2 crossing the first direction D1.Each of the standard cells SC may include a P-well region PR where NMOSfield effect transistors are formed and an N-well region NR where PMOSfield effect transistors are formed.

FIG. 2 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts. FIGS. 3A, 3B, 3C, and3D illustrate cross-sectional views respectively taken along lines I-I′,and IV-IV′ of FIG. 2.

Referring to FIGS. 2 and 3A to 3D, a semiconductor substrate 100 may beprovided thereon with a plurality of standard cells SC arranged along afirst direction D1. Each of the standard cells SC may include activepatterns 101, gate structures GS, source/drain impurity layers 130,active contact patterns ACP1 and ACP2, gate contact patterns GCP, viapatterns VP1 and VP2, wiring patterns CP, and power lines PL1 and PL2.The term “contact pattern” or the term “contact,” as used herein, mayrefer to one of the active contact patterns ACP1 or ACP2. Moreover, asused herein, the term “connection pattern” or the term “connector” mayrefer to a via pattern VP, a via pattern VP1, or a via pattern VP2.

The semiconductor substrate 100 may include first and second wellregions R1 and R2. In some embodiments, NMOS field effect transistorsmay be provided on the first well region R1, and PMOS field effecttransistors may be provided on the second well region R2.

The semiconductor substrate 100 may be, for example, a siliconsubstrate, a germanium substrate, an SOI (Silicon On Insulator)substrate, or a GOI (Germanium On Insulator) substrate. At/in each ofthe first and second well regions R1 and R2, a plurality of the activepatterns 101 may extend in the first direction D1, and may be spacedapart from each other in a second direction D2 crossing the firstdirection D1. The active patterns 101 may be portions of thesemiconductor substrate 100 and may be defined by trenches formed in thesemiconductor substrate 100.

A first device isolation layer 103 may be disposed between the activepatterns 101, and upper portions of the active patterns 101 may beexposed by the first device isolation layer 103. For example, the firstdevice isolation layer 103 may have a top surface below those of theactive patterns 101, and the active patterns 101 may protrude upwardbeyond the top surface of the first device isolation layer 103. Thefirst device isolation layer 103 may separate the active patterns 101from each other in the second direction D2.

A second device isolation layer 105 may extend in the first direction D1and may define the first well region R1 and the second well region R2.The second device isolation layer 105 may be provided between the activepatterns 101 of the first well region R1 and the active patterns 101 ofthe second well region R2. The second device isolation layer 105 mayhave a width greater than that of the first device isolation layer 103.The second device isolation layer 105 may have a bottom surface at alevel lower than or substantially the same as that of a bottom surfaceof the first device isolation layer 103. The second device isolationlayer 105 may separate the first and second well regions R1 and R2 fromeach other in the second direction D2. The first and second deviceisolation layers 103 and 105 may be formed by forming trenches definingthe active patterns 101 and filling portions of the trenches with aninsulating material (e.g., a silicon oxide layer or a silicon nitridelayer).

The gate structures GS may extend in the second direction D2, whilecrossing the active patterns 101 of the first and second well regions R1and R2. The gate structures GS may be regularly arranged at a firstpitch at/in each of the standard cells SC. For example, the gatestructures GS may have substantially the same first width W1, and may beequally spaced apart from each other in the first direction D1 at afirst spacing S1.

Each of the gate structures GS may include a gate dielectric layer 111,a gate barrier metal pattern 113, a gate metal pattern 115, and acapping insulation pattern 117. Gate spacers 121 may be disposed onopposite sidewalls of each of the gate structures GS.

The gate dielectric layer 111 may extend along the second direction D2,and may conformally cover upper portions of the active patterns 101. Thegate dielectric layer 111 may extend from between the gate barrier metalpattern 113 and the active patterns 101 to between the gate barriermetal pattern 113 and the gate spacers 121. For example, the gatedielectric layer 111 may extend from a bottom surface of the gate metalpattern 115 to opposite sidewalls of the gate metal pattern 115. Thegate dielectric layer 111 may include a high-k dielectric material whosedielectric constant is greater than that of silicon oxide. The gatedielectric layer 111 may include, for example, metal oxide, metalsilicate, or metal silicate nitride.

The gate barrier metal pattern 113 may be disposed between the gatedielectric layer 111 and the gate metal pattern 115, and may extendbetween the gate metal pattern 115 and the gate spacers 121. The gatebarrier metal pattern 113 may include conductive metal nitride (e.g.,titanium nitride, tantalum nitride, and/or tungsten nitride). The gatemetal pattern 115 may include a metallic material (e.g., tungsten,titanium, and/or tantalum). The capping insulation pattern 117 may covera top surface of the gate metal pattern 115. The capping insulationpattern 117 may also cover top surfaces of the gate spacers 121. Thecapping insulation patterns 117 may have top surfaces substantiallycoplanar with that of a gap-fill insulation layer 131. The cappinginsulation patterns 117 and the gate spacers 121 may include, forexample, silicon oxide, silicon nitride, silicon oxynitride, siliconcarbon nitride (SiCN), or silicon carbon oxynitride (SiCON).

According to some embodiments, a third device isolation layer 107 mayextend parallel to the gate structures GS in the second direction D2,and may be disposed between ones of (e.g., a pair of) the standard cellsSC that are adjacent to each other. The third device isolation layer 107may cross the active patterns 101 in the second direction D2, and mayseparate the active patterns 101 from each other in the first directionD1. The third device isolation layer 107 may separate field effecttransistors that are adjacent to each other in the first direction D1.The third device isolation layer 107 may include, for example, a siliconoxide layer, a silicon nitride layer, a silicon oxynitride layer, asilicon carbon nitride (SiCN) layer, a silicon carbon oxynitride (SiCON)layer, or a combination thereof. For example, the third device isolationlayer 107 may include a silicon nitride and/or a silicon oxide layer.

The third device isolation layer 107 may be disposed between ones of(e.g., a pair of) the gate structures GS that are adjacent to eachother. For example, the third device isolation layer 107 may be spacedapart at a second spacing S2 from the gate structures GS disposed atedges of the standard cells SC. In some embodiments, the second spacingS2 may be substantially the same as the first spacing 51. The thirddevice isolation layer 107 may have a second width W2 less than abouttwice (i.e., double) the first width W1 of the gate structures GS. Forexample, the second width W2 of the third device isolation layer 107 maybe substantially the same as the first width W1 of the gate structuresGS.

The third device isolation layer 107 may have an upper portion thatprotrudes upward beyond the active patterns 101 and penetrates portionsof the active patterns 101. The third device isolation layer 107 mayhave a top surface lower than those of the gate structures GS and higherthan those of the active patterns 101. The third device isolation layer107 may have a bottom surface at a level lower than or substantially thesame as that of the bottom surface of the first or second deviceisolation layer 103 or 105.

Dummy spacers 123 may be disposed on opposite sidewalls of the upperportion of the third device isolation layer 107. In some embodiments,the dummy spacers 123 may include an insulating material the same asthat of the gate spacers 121. The dummy spacers 123 may have topsurfaces lower than those of the gate spacers 121. For example, thedummy spacers 123 may have a height less than that of the gate spacers121.

The source/drain impurity layers 130 may be disposed on the activepatterns 101 on opposite sides of each of the gate structures GS. Thesource/drain impurity layers 130 of the first well region R1 may includen-type impurities, and the source/drain impurity layers 130 of thesecond well region R2 may include p-type impurities. The source/drainimpurity layers 130 may be epitaxial layers grown from the activepatterns 101. The source/drain impurity layers 130 of the first wellregion R1 may be germanium (Ge) epitaxial layers, and the source/drainimpurity layers 130 of the second well region R2 may be silicon carbide(SiC) epitaxial layers. According to some embodiments, the third deviceisolation layer 107 may separate, from each other, the source/drainimpurity layers 130 that are adjacent to each other in the firstdirection D1 at edges of the standard cells SC. The source/drainimpurity layers 130 formed by epitaxial growth may be connected to eachother in the second direction D2, as illustrated in FIG. 3D. As usedherein, the term “source/drain impurity region” may refer to one of thesource/drain impurity layers 130.

The gap-fill insulation layer 131 may fill a space between the gatestructures GS and may cover the source/drain impurity layers 130. Insome embodiments, the top surface of the gap-fill insulation layer 131may be substantially coplanar with the top surfaces of the gatestructures GS. The gap-fill insulation layer 131 may cover the topsurface of the third device isolation layer 107.

In some embodiments, before the gap-fill insulation layer 131 is formed,an etch stop layer 135 may be formed to have a substantially uniformthickness. The etch stop layer 135 may extend onto the source/drainimpurity layers 130 from sidewalls of the gate spacers 121. The etchstop layer 135 may extend onto sidewalls of the capping insulationpattern 117 from the sidewalls of the gate spacers 121.

An interlayer insulation layer 133 may be disposed on the gap-fillinsulation layer 131 and may cover the top surfaces of the gatestructures GS. The gap-fill insulation layer 131 and the interlayerinsulation layer 133 may be formed of an insulating material having anetch selectivity to the gate spacers 121, and may include one or more ofa silicon oxide layer, a silicon nitride layer, a silicon oxynitridelayer, and a low-k dielectric layer.

The active contact patterns ACP1 and ACP2 may penetrate the interlayerinsulation layer 133, the gap-fill insulation layer 131, and the etchstop layer 135, and may be connected to the source/drain impurity layers130. In some embodiments, the active contact patterns ACP1 and ACP2 mayinclude first active contact patterns ACP1, which lie between the thirddevice isolation layer 107 and its adjacent gate structures GS, andsecond active contact patterns ACP2, which lie between ones of the gatestructures GS that are adjacent to each other.

Each of the active contact patterns ACP1 and ACP2 may be connectedeither to one source/drain impurity layer 130 or to a plurality of thesource/drain impurity layers 130 disposed in the second direction D2.The active contact patterns ACP1 and ACP2 may include a first metallicmaterial, for example, metal (e.g., tungsten, titanium, or tantalum)and/or conductive metal nitride (e.g., titanium nitride, tantalumnitride, or tungsten nitride). Each of the active contact patterns ACP1and ACP2 may include a first barrier metal layer 141 and a first metallayer 143. The first barrier metal layer 141 of the active contactpatterns ACP1 and ACP2 may have a uniform thickness, and may conformallycover a top surface of the source/drain impurity layer 130.

The gate contact patterns GCP may penetrate the interlayer insulationlayer 133, the gap-fill insulation layer 131, and the capping insulationpatterns 117 of the gate structures GS, and may be connected to the gatemetal patterns 115. The gate contact patterns GCP may be formedsimultaneously with the active contact patterns ACP1 and ACP2, and mayinclude the same first metallic material as that of the active contactpatterns ACP1 and ACP2. Like the active contact patterns ACP1 and ACP2,each of the gate contact patterns GCP may include the first barriermetal layer 141 and the first metal layer 143. The first barrier metallayer 141 of the gate contact patterns GCP may have a uniform thickness,and may be interposed between the first metal layer 143 and the gatemetal pattern 115. The gate contact patterns GCP may have top surfacessubstantially coplanar with those of the active contact patterns ACP1and ACP2.

A first etch stop layer 151 and a first interlayer dielectric layer 153may be sequentially stacked on the interlayer insulation layer 133. Thefirst etch stop layer 151 may cover the top surfaces of the activecontact patterns ACP1 and ACP2 and the top surfaces of the gate contactpatterns GCP. The first etch stop layer 151 may include, for example,silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC),silicon carbon nitride (SiCN), or a combination thereof. The firstinterlayer dielectric layer 153 may include a dielectric material whosedielectric constant is lower than that of a silicon oxide layer.

The via patterns VP1 and VP2 may be formed in the first interlayerdielectric layer 153 and the first etch stop layer 151, and may beconnected to the active contact patterns ACP1 and ACP2. The via patternsVP1 and VP2 may include a second metallic material different from thefirst metallic material, and the second metallic material may haveresistivity less than that of the first metallic material. For example,the second metallic material may include copper or its alloy. In thisdescription, the copper alloy may mean copper mixed with an extremelysmall amount of one of Carbon (C), Silver (Ag), Cobalt (Co), Tantalum(Ta), Indium (In), Tin (Sn), Zinc (Zn), Manganese (Mn), Titanium (Ti),Magnesium (Mg), Chromium (Cr), Germanium (Ge), Strontium (Sr), Platinum(Pt), Aluminum (Al), and Zirconium (Zr). Each of the via patterns VP1and VP2 may include a second barrier metal layer 161 and a second metallayer 163, and the second barrier metal layer 161 may be interposedbetween the second metal layer 163 and the active contact pattern ACP1or ACP2.

According to some embodiments, the via patterns VP1 and VP2 may includefirst via patterns VP1 connected to the first active contact patternACP1 and second via patterns VP2 connected to the second active contactpattern ACP2. For example, the first via pattern VP1 and the firstactive contact pattern ACP1 may be electrically connected to each otherat an edge of each of the standard cells SC, and the second via patternVP2 and the second active contact pattern ACP2 may be electricallyconnected to each other at an inner region of each of the standard cellsSC.

According to some embodiments, each of the first via patterns VP1 mayhave a bar shape whose major axis extends in the first direction D1 onthe first active contact pattern ACP1. For example, the first viapattern VP1 may have a length in the first direction D1 greater than awidth in the first direction D1 of the first active contact patternACP1. As viewed in plan, the first via patterns VP1 may overlap aportion of the gate structure GS. The first via pattern VP1 may have onesidewall spaced apart at a first distance d1 in the first direction D1from an axis aligned with a sidewall of the third device isolation layer107.

In some embodiments, the first via patterns VP1 of neighboring standardcells SC may be adjacent to each other across the third device isolationlayer 107. The first via patterns VP1 may be spaced apart from eachother in the first direction D1 at a second distance d2 greater than thesecond width W2 of the third device isolation layer 107.

A second etch stop layer 171 and a second interlayer dielectric layer173 may be sequentially stacked on the first interlayer dielectric layer153. The second etch stop layer 171 and the second interlayer dielectriclayer 173 may cover top surfaces of the first and second via patternsVP1 and VP2. For example, the second etch stop layer 171 and the secondinterlayer dielectric layer 173 may be formed after the first and secondvia patterns VP1 and VP2 are formed.

At/in each of the standard cells SC, the wiring patterns CP may bedisposed in the second etch stop layer 171 and the second interlayerdielectric layer 173, and may be connected to the first and second viapatterns VP1 and VP2. The wiring patterns CP may include a thirdmetallic material whose resistivity is less than that of the firstmetallic material. In some embodiments, the third metallic material maybe the same as the second metallic material, and may include, forexample, copper or its alloy. The wiring patterns CP may include a thirdbarrier metal layer 181 and a third metal layer 183. The third barriermetal layer 181 may be interposed between the third metal layer 183 ofthe wiring pattern CP and the second metal layer 163 of the first orsecond via pattern VP1 or VP2. In this configuration, an interface mayexist between the wiring patterns CP and the via patterns VP1 and VP2.

In some embodiments, the wiring pattern CP may connect one first viapattern VP1 to another first via pattern VP1 spaced apart from the onefirst via pattern VP1, or may connect the first via pattern VP1 to thesecond via pattern VP2. Each of the wiring patterns CP may extend in thefirst direction D1, and may include a first segment connected to thefirst active contact pattern ACP1. Each of the wiring patterns CP mayfurther include a second segment that extends in the second direction D2from the first segment.

In some embodiments, the first segment of the wiring pattern CP may runacross the gate structure GS. The wiring pattern CP may have onesidewall spaced apart from an axis that is aligned with a sidewall ofthe third device isolation layer 107 in the first direction D1 at athird distance d3 greater than the first distance d1. For example, theone sidewall of the wiring pattern CP may be spaced farther apart fromthe axis that is aligned with the third device isolation layer 107 thanis the one sidewall of the first via pattern VP1. The one sidewall ofthe first via pattern VP1 may be spaced apart in the first direction D1from an axis aligned with the one sidewall of the wiring pattern CP. Thewiring pattern CP may be in contact with a portion of the first viapattern VP1, and with an entire top surface of the second via patternVP2. For example, the portion of the first via pattern VP1 that thewiring pattern CP contacts may be only a first portion of the first viapattern VP1, such that a second portion of the first via pattern VP1 isfree of the wiring pattern CP.

The wiring patterns CP of the standard cells SC may be spaced apart fromeach other across the third device isolation layer 107 in the firstdirection D1 at a fourth distance d4. The fourth distance d4 may begreater than the second distance d2. Namely, the fourth distance d4between the wiring patterns CP adjacent to each other in the firstdirection D1 may be greater than the second distance d2 between thefirst via patterns VP1 adjacent to each other in the first direction D1.

The first power line PL1 and the second power line PL2 may extend in thefirst direction D1, and may be connected in common to the standard cellsSC. The first power line PL1 may be spaced apart in the second directionD2 from the second power line PL2. The first and second power lines PL1and PL2 may each be electrically connected through the via patterns VP1and VP2 to at least a corresponding one of the active contact patternsACP1 and ACP2.

According to some embodiments, even if the gate structures GS decreasein pitch and the third device isolation layer 107 decreases in width, aprocess margin may be secured to the wiring patterns CP adjacent to eachother in the first direction D1. In addition, as the first via patternsVP1 have a bar shape whose major axis extends in the first direction D1,a contact area may be securely provided between the wiring pattern CPand the first via pattern VP1.

FIG. 4 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts. FIG. 5 illustrates across-sectional view taken along line I-I′ of FIG. 4. FIG. 6 illustratesa plan view showing a semiconductor device according to exampleembodiments of the inventive concepts. Descriptions of the sametechnical features as those of the embodiments discussed with referenceto FIGS. 2 and 3A to 3D may be omitted in the interest of brevity ofdescription.

Referring to FIGS. 4 and 5, the first active contact patterns ACP1adjacent to the third device isolation layer 107 may not overlap thegate structures GS, in plan view. For example, the first via pattern VP1may be disposed between the third device isolation layer 107 and itsadjacent gate structure GS. The first via pattern VP1 may have a widthin the first direction D1 less than a spacing S2 between the thirddevice isolation layer 107 and its adjacent gate structure GS.

Referring to FIG. 6, a semiconductor device may be provided with viapatterns that include a first via pattern VP1 connected to the firstactive contact pattern ACP1, a second via pattern VP2 connected to thesecond active contact pattern ACP2, and a third via pattern VP3connected to the gate contact pattern GCP. The first to third viapatterns VP1, VP2, and VP3 may each have a bar shape whose major axisextends in the first direction D1.

In some embodiments, one of the wiring patterns CP may extend parallelto the third device isolation layer 107 in the second direction D2, andmay be electrically connected through the first via patterns VP1 to thefirst active contact patterns ACP1.

Alternatively, the wiring pattern CP may connect the first via patternVP1 adjacent to the third device isolation layer 107 to the third viapattern VP3 connected to the gate structure GS. The wiring pattern CPmay have one sidewall, which may be spaced farther apart from the thirddevice isolation layer 107 than one sidewall of the first via patternVP1 and which may be in contact with a portion of the first via patternVP1.

FIGS. 7, 9, and 11 illustrate plan views showing a portion of asemiconductor device according to example embodiments of the inventiveconcepts. FIGS. 8, 10, and 12 illustrate cross-sectional views takenalong line I-I′ of FIGS. 7, 9, and 11, respectively. Descriptions of thesame technical features as those of the embodiments discussed withreference to FIGS. 2 and 3A to 3D may be omitted in the interest ofbrevity of description.

Referring to FIGS. 7 and 8, first and second ones of (i.e., a pair of)the first via patterns VP1 adjacent to each other across the thirddevice isolation layer 107 may be spaced apart from each other at asecond distance d2, and the wiring patterns CP adjacent to each otheracross the third device isolation layer 107 may be spaced apart fromeach other at a fourth distance d4. The fourth distance d4 may besubstantially equal to or greater than the second distance d2.

Referring to FIGS. 9 and 10, the first via patterns VP1 may be spacedapart from each other in the first direction D1 at a second distance d2,and the wiring patterns CP may be spaced apart from each other at afourth distance d4 greater than the second distance d2. In addition,each of the first via patterns VP1 may extend in the first direction D1and may overlap a portion of the gate structure GS.

As viewed in plan view, each of the wiring patterns CP may be in contactwith a portion of the first via pattern VP1, and may not overlap thefirst active contact pattern ACP1. Because an increased spacing isprovided between the wiring patterns CP as well as contact areas aresecured between the wiring patterns CP and the first via patterns VP1,even if the standard cells SC decrease in area, a process margin may besecured to the wiring patterns CP.

Referring to FIGS. 11 and 12, each of the first via patterns VP1 may runacross at least one gate structure GS, and may extend onto the secondactive contact pattern ACP2 from the first active contact pattern ACP1.In this configuration, each of the first via patterns VP1 mayelectrically connect the first active contact pattern ACP1 to the secondactive contact pattern ACP2.

FIG. 13 illustrates a plan view showing a semiconductor device accordingto example embodiments of the inventive concepts. FIG. 14 illustrates across-sectional view taken along line I-I′ of FIG. 13. Descriptions ofthe same technical features as those of the embodiments discussed withreference to FIGS. 2 and 3A to 3D may be omitted in the interest ofbrevity of description.

Referring to FIGS. 13 and 14, the gate structures GS may extend in thesecond direction D2, while crossing the active patterns 101 that extendin the first direction D1. The gate structures GS may have substantiallythe same first width W1, and may be equally spaced apart from each otherin the first direction D1 at a first spacing S1.

A fourth device isolation layer 109 may separate the active patterns 101from each other in the first direction D1 at an edge of the standardcell SC. In some embodiments, the fourth device isolation layer 109 mayhave a width W3 greater than the first spacing S1 between neighboringgate structures GS.

Dummy gate structures DGS may be disposed at the edge of the standardcell SC and at a boundary between the fourth device isolation layer 109and the active patterns 101. The dummy gate structures DGS may have astack structure the same as that of the gate structures GS.

The active contact patterns ACP1 and ACP2 may be connected to thesource/drain impurity layers 130 on opposite sides of each of the gatestructures GS. As discussed above, the active contact patterns ACP1 andACP2 may include first active contact patterns ACP1, which lie betweenthe fourth device isolation layer 109 and its adjacent gate structuresGS, and second active contact patterns ACP2, which lie between ones ofthe gate structures GS that are adjacent to each other.

In some embodiments, the via patterns VP may be connected to the activecontact patterns ACP1 and ACP2, and one of the via patterns VP mayelectrically connect a plurality of (e.g., a pair of) the second activecontact patterns ACP2 to each other. The one of the via patterns VP mayextend in the first direction D1 to run across the gate structure GS,and may be in direct contact with the plurality of second active contactpatterns ACP2.

As discussed above, the active contact patterns ACP1 and ACP2 mayinclude a first metallic material, and the via patterns VP may include asecond metallic material whose resistivity is less than that of thefirst metallic material.

According to example embodiments of the inventive concepts, compared tothe via patterns, the wiring patterns may be spaced farther apart in thefirst direction from the device isolation layer at a boundary betweenthe standard cells. Accordingly, even if a spacing between the standardcells is decreased due to a width reduction of the device isolationlayer, a process margin is secured to the wiring patterns. The viapattern may have a bar shape whose major axis extends in the firstdirection, such that a contact area may be securely provided between thewiring pattern and the via pattern.

The via pattern and the wiring pattern that are connected to thestandard cell may be formed of a metallic material having a lowerresistivity, thereby decreasing resistance between connection linesconnected to the standard cell.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope. Thus, to the maximum extent allowed by law,the scope is to be determined by the broadest permissible interpretationof the following claims and their equivalents, and shall not berestricted or limited by the foregoing detailed description.

What is claimed is:
 1. A semiconductor device comprising: a plurality ofactive patterns extending in a first direction; a device isolation layercrossing the plurality of active patterns and extending in a seconddirection crossing the first direction; a gate structure spaced apartfrom the device isolation layer and extending in the second direction tocross the plurality of active patterns; a plurality of source/drainimpurity layers adjacent opposite sides of the gate structure; a contactpattern connected to one of the plurality of source/drain impuritylayers that is between the device isolation layer and the gatestructure; a connection pattern connected to the contact pattern, theconnection pattern including a first barrier metal layer and a firstmetal layer; and a wiring pattern connected to the connection pattern,the wiring pattern including a second barrier metal layer and a secondmetal layer, wherein the second barrier metal layer is between a topsurface of the first metal layer and a bottom surface of the secondmetal layer.
 2. The semiconductor device of claim 1, wherein theconnection pattern has a first sidewall spaced apart by a first distancein the first direction from the device isolation layer; and wherein thewiring pattern has a second sidewall spaced apart in the first directionfrom the device isolation layer by a second distance that is greaterthan the first distance.
 3. The semiconductor device of claim 1, whereinthe gate structure is spaced apart from the device isolation layer inthe first direction by a spacing distance, and wherein the connectionpattern has a width less than the spacing distance, in the firstdirection.
 4. The semiconductor device of claim 1, wherein theconnection pattern has a length less than a length of the contactpattern, in the second direction.
 5. The semiconductor device of claim1, wherein the wiring pattern extends along the first direction to crossthe gate structure.
 6. The semiconductor device of claim 1, wherein theconnection pattern and the wiring pattern comprise the same metallicmaterial.
 7. The semiconductor device of claim 1, wherein the contactpattern comprises a first metallic material, and wherein the connectionpattern and the wiring pattern comprise a second metallic materialcomprising a resistivity that is lower than a resistivity of the firstmetallic material.
 8. The semiconductor device of claim 1, wherein thedevice isolation layer has a width that is substantially equal to awidth of the gate structure.
 9. The semiconductor device of claim 1,wherein the device isolation layer has a width in the first directionthat is shorter than a distance in the first direction between thedevice isolation layer and the gate structure adjacent the deviceisolation layer.
 10. The semiconductor device of claim 1, wherein thefirst metal layer has a first sidewall adjacent to the device isolationlayer and the second metal layer has a second sidewall adjacent to thedevice isolation layer, wherein the first barrier metal layer includes afirst sidewall portion covering the first sidewall of the first metallayer and the second barrier metal layer includes a second sidewallportion covering the second sidewall of the second metal layer, andwherein the second sidewall portion of the second barrier metal layer islaterally spaced apart from the first sidewall portion of the firstbarrier metal layer.
 11. The semiconductor device of claim 10, furthercomprising an insulating layer on the connection pattern and covering atop surface of the first sidewall portion of the first barrier metallayer.
 12. A semiconductor device comprising: a substrate comprising aplurality of active patterns extending in a first direction; a deviceisolation layer crossing the plurality of active patterns and extendingin a second direction crossing the first direction; a gate structurespaced apart from the device isolation layer and extending in the seconddirection to cross the plurality of active patterns; first and secondimpurity layers on the substrate adjacent opposite first and secondsides, respectively, of the gate structure, wherein the first impuritylayer is between the device isolation layer and the gate structure; afirst contact pattern connected to the first impurity layer that isbetween the device isolation layer and the gate structure; a secondcontact pattern connected to the second impurity layer; a connectionpattern connected to the first contact pattern; and a wiring patternconnected to the connection pattern and overlapping both the first andsecond contact patterns.
 13. The semiconductor device of claim 12,wherein a width of the connection pattern is greater than a width of thefirst contact pattern, in the first direction.
 14. The semiconductordevice of claim 12, wherein the connection pattern has a first sidewallspaced apart by a first distance in the first direction from the deviceisolation layer; and wherein the wiring pattern has a second sidewallspaced apart in the first direction from the device isolation layer by asecond distance that is greater than the first distance.
 15. Thesemiconductor device of claim 12, wherein the first and second contactpatterns comprise a first metallic material, wherein the connectionpattern and the wiring pattern comprise a second metallic materialdifferent from the first metallic material.
 16. The semiconductor deviceof claim 12, wherein the connection pattern has a width less than adistance between the device isolation layer and the gate structureadjacent to the device isolation layer.
 17. The semiconductor device ofclaim 12, wherein the wiring pattern extends in the first direction andcontacts a portion of a top surface of the connection pattern.
 18. Thesemiconductor device of claim 12, wherein the gate structure includes: agate dielectric layer; a gate barrier metal pattern on the gatedielectric layer; a gate metal pattern on the gate barrier metalpattern; and a capping insulation pattern on the gate metal pattern,wherein a top surface of the device isolation layer is located atsubstantially the same level as a top surface of the gate metal pattern.19. The semiconductor device of claim 12, wherein the connection patterncomprises: a first barrier metal layer; and a first metal layer on thefirst barrier metal layer, and wherein the wiring pattern comprises: asecond barrier metal layer that contacts a top surface of the firstmetal layer; and a second metal layer on the second barrier metal layer.20. The semiconductor device of claim 19, wherein the first metal layerand the second metal layer comprise the same metallic material.